As the demands for video signal processing, digital signal synthesis, and high-accuracy digital-to-analog converters (DACs) generate an increased need for higher clock frequencies and dynamic ranges, CMOS current-steering DAC architectures provide the best structure for most of these applications. CMOS current-steering DACS may be integrated within digital circuits to yield systems that have cost and power consumption advantages. Furthermore, CMOS current-steering DACS are intrinsically faster and more linear than competing architectures such as resistor-string DACs.
Conversion from digital-to-analog (D/A) is the process of converting digital codes into a continuous range of analog signal levels. Digital codes are typically converted to analog voltages by assigning a voltage weight, or current weight, to each bit in the digital code and summing the voltage or current weights of the entire code. A digital-to-analog converter (DAC) having weights using the power of two is called a binary weighted DAC. Resistor-string DACs are DACs that produce a voltage output. Current-steering DACs are DACs that produce analog current outputs.
Current-steering DACs are implemented using an array of matched current sources which are unity decoded or binary weighted. There are a variety of architectures in which a current-steering DACs may be implemented from two-stage, interpolated, or segmented architectures. Random mismatches between each the current source, however, present a problem of intrinsic inaccuracy.
For simplicity, a 3-bit current-steering DAC using thermometer decoding is depicted in FIG. 1. As shown the 3-bit current-steering DAC is a structure that is implemented with current sources that are connected to PMOS output switches. In general, the unit current source is normalized to 1. The digital inputs are clocked into the decoder 102. The decoder 102 translates the input digital code to a corresponding control code (S1–S7, R1–R7) that steers the current sources to the output across resistors R10 and R20. Latch 104 captures these control codes (S1–S7, R1–R7) to generate a second set of control codes (Y1–Y7, Y1B–Y7B). Assuming the current sources are ideal, the output current is proportional to the input digital control word. In the alternative, current-steering DAC architectures can also be implemented using current sinks and NMOS output switches. In general, the output switches are either off or in the saturation region during switching in order to reduce the settling time. The timing diagram and transfer curve of the output versus input code sweep is shown in FIG. 2. In operation, as shown there is a point in time when the switches that generate the second set of control codes (Y1–Y7, Y1B–Y7B) are simultaneously off. At this point, there will be a glitch in the output current as shown in FIG. 2.
Major factors that determine the quality of performance of DACs are resolution, sampling rate, speed, and linearity. The accuracy of the DAC's measurement and conversion is typically specified by the converter's linearity. “Integral linearity” is a measure of linearity over the entire conversion range. It is defined as the deviation from a straight line drawn between the maximum point and through zero (or the offset value) of the conversion range. “Differential linearity” is the linearity between adjacent steps of the analog output. In addition, differential linearity is a measure of the monotonicity of the converter. The converter is said to be monotonic if increasing input values result in increasing output values. As stated previously, current-steering DACs usually have a faster settling time and better linearity than those resistor-string DACs.
Within a current-steering DAC, static errors, such as differential nonlinearity (DNL) and integral nonlinearity (INL), are caused by the mismatch among the unit current sources. Dynamic nonlinearity, such as spurious-free dynamic range (SFDR), is associated with current-source switching and settling. Dynamic nonlinearity is caused by various factors including, but not limited to (1) an imperfect synchronization of the input signals, (2) current variation due to a drain voltage variation of the current sources, (3) crosstalk between a new input digital code and control signals latched from the previous input digital code, or (4) the interference generated by the clock signal which is feed through to the output.
FIG. 3 represents a unit cell 300 from the current steering DAC 100 of FIG. 1, whereas FIG. 4 displays the conventional switch-driving scheme and drain voltage variations. As shown, the crossing point of the control signals is in the middle of the high voltage (VH) and the low voltage (VL). At the crossing point, the output switches, 302 and 304, are both off. During the switching from the output (IOUT) to the complementary output (IOUTB), the output switches, 302 and 304, can be both off for some time, this is equivalent to a high output impedance current source having no valid output voltage, therefore the drain voltage Vx at node X can have a variation ΔVx. This variation not only impacts the accuracy of the output through channel length modulation, but also impacts the settling of the output which leads to the harmonic distortion and degradation of the SFDR. In order to reduce the variation, it is preferred to have a switch crossover point where there is no time when both switches are off.
Another approach as shown in FIG. 5 is a delayed driving scheme which reduces the variation of the drain node voltage. The input synchronization is realized by using two traditional latches as implemented using switches 504, 506, 508, and 510 in front of the delayed driving block. As shown in FIG. 6, the crossing points are lower than the middle point (VH+VL)/2 for PMOS output switches, 514 and 516; while the crossing points are higher than the middle point (VH+VL)/2 for NMOS output switches, 302 and 304 of FIGS. 3 and 4.
FIGS. 7 and 8 illustrate another current-steering DAC having a driving scheme that uses ratio logic latching to generate similar complementary control signals, Y and YB. In operation, when the clock signal CLK is low, the outputs do not change. When the clock signal CLK switches to high, complementary inputs SEL and SELB are latched in and the output propagates to the current switches, 712 and 714. Due to intrinsic delay, the outputs crossover at a point lower than the middle point. This is useful when driving PMOS output transistors as displayed in FIG. 8. It is easy to flip the structure to have crossing point higher than the middle point and drive NMOS output switches, 712 and 714. This latch architecture, however, suffers from a cross-talk problem where the new inputs to the latch during the clock signal CLK low period leak to the outputs where a previous value is stored. If SEL and SELB change when the clock signal CLK is low, a glitch will appear at the latch outputs as is shown in FIG. 9. As a result, signal dependent current error is induced at the current source outputs, Y and YB. This glitch energy is related to input frequency and causes harmonic distortion and SFDR degradation.
A third implementation of a current-steering DAC is illustrated in FIG. 10. An acceptable crossing point of its output is achieved using fast rising and falling times instead of the uses of an intrinsic delay as illustrated by the structure in FIG. 7. The advantage is a higher performance speed. In addition to higher speed, the unwanted crosstalk is reduced by the NMOS switches, s1 and s2. Clock feed through is suppressed by the cross-coupled weak inverters implemented using switches 814, 816, 818, and 820, following the switches, s1 and s2. If the new inputs SEL and SELB are different from the old inputs being held by the inverters 814, 816, 818, and 820, there will be a conflict between the new inputs and the previous input held by the inverters 814, 816, 818, and 820. The number of code conflicts depends upon the difference between the old and new inputs. This contention causes asynchronous switching between the current cells which degrades the SFDR. As a result, the holding inverters, 814, 816, 818, and 820, must be much weaker than the decoder driver (not shown).
The present invention is directed to overcoming, or at least reducing the effects of one or more of the problems set forth above.